(China (Mainland))
Product Summary
The 74HC374PW is a high-speed Si-gate CMOS device. It is pin compatible with low power Schottky TTL (LSTTL). The device is specified in compliance with JEDEC standard no. 7A. The 74HC374PW is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 74HC374PW will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 74HC374 are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
Parametrics
74HC374PW absolute maximum ratings: (1)propagation delay CP to Qn:15ns; (2)maximum clock frequency: 77MHz; (3)input capacitance: 3.5pF; (4)power dissipation capacitance per flip-flop: 17pF.
Features
74HC374PW features: (1)3-state non-inverting outputs for bus oriented applications; (2)8-bit positive, edge-triggered register; (3)Common 3-state output enable input; (4)Independent register and 3-state buffer operation; (5)Output capability: bus driver; (6)ICC category: MSI.
Diagrams
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 74HC374PW |
NXP Semiconductors |
Flip Flops OCTAL D 3-S |
Data Sheet |
Negotiable |
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74HC374PW,112 |
NXP Semiconductors |
Flip Flops OCTAL D 3-S |
Data Sheet |
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74HC374PW,118 |
NXP Semiconductors |
Flip Flops OCTAL D 3-S |
Data Sheet |
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